For nanometer designs, accurate simulation and analysis requires more than traditional resistance and capacitance. Designers need a post-layout silicon model that incorporates inductance, process sensitivity effects, and efficient accounting of effects not captured in the device model. Using Calibre xRC and Calibre xL in the design flow helps ensure that designers have all the data they need to obtain successful first pass silicon.
“We have developed testing methodology for parasitic extraction tools to make sure we deliver accurate solutions to our customers. Calibre xRC and Calibre xL performed well in our internal tests and offer advanced modeling capabilities to capture process variation effects that are necessary for 65nm,” said Ed Wan, senior director of design services marketing, TSMC.
“Delivering accurate, complete parasitic models is an integral part of Calibre’s overall objective to improve silicon yield,” said Joe Sawicki, vice president and general manager, Design to Silicon Division, Mentor Graphics. “When coupled with Calibre LVS for device modeling, Calibre xRC and Calibre xL help designers address parametric yield issues by accurately capturing process variation effects in device and interconnect models. Additionally, customers now have access to a full complement of inductance models with self, mutual and skin effect modeling that is necessary for today’s high frequency interconnect.”
Enabling Accurate Post-Layout Functional Verification:
The New Nanometer Silicon Model
Shrinking geometries and increasing design size in the nanometer era have enabled greater functionality on a single chip. But with the increased functionality comes new complexities that create more problems in the attempt to attain design closure. This requires an electrical representation of the chip that accounts for the actual physical design of its devices and interconnect, and accurate silicon model. Calibre xRC and Calibre xL meet the demands of nanometer designs with a comprehensive approach to device and parasitic extraction to compose accurate silicon models enabling a large variety of post-layout analyses.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $750 million and employs approximately 4,100 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
Mentor Graphics and Calibre are registered trademarks and xRC is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
